[J9] X. Zhao, R. Xu, Y. Gao, V. Verma, M. Stan, X. Guo*, “Edge-MPQ: Layer-Wise Mixed-Precision Quantization with Tightly Integrated Versatile Inference Units for Edge Computing”, IEEE Transactions on Computers (TC), 2024, To appear. (link)
[J8] J. Shaik, X. Guo*, S. Singhal, “Impact of Aging and Process Variability on SRAM-based In-Memory Computing Architectures”, IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2024, To appear. (link)
[J7] X. Guo*, “Active Accelerated Recovery for Combating Chip Aging Issues – Opportunities and Challenges”, Journal of Electronics & Information Technology, vol. 45, no. 11, pp. 1-12, 2023. (Invited paper) (In Chinese) (Featured Article)
[J6] M. El-Hadedy⋄*, X. Guo⋄*, K. Yoshii, Y. Cai, R. Herndona, B. Bantaa, W. Hwu, “RECO-ASCON: Reconfigurable ASCON Hash Functions for IoT Applications”, Integration, the VLSI Journal, vol. 93, pp. 102061, 2023. (⋄ Equal contributions)
[J5] X. Guo*, M. El-Hadedy, S. Mosanu, X. Wei, K. Skadron, M. Stan, “Agile-AES: Implementation of Configurable AES Primitive with Agile Design Approach”, Accepted by Integration, the VLSI Journal, 2022. (link)
[J4] P. Guerrero, T. Tracy II, X. Guo, M. Lenjani, K. Skadron and M. Stan, “Towards on-node machine learning for ultra-low-power sensors using asynchronous Sigma Delta streams,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 16, No. 4, Article 44 , doi.org/10.1145/3404975, 2020. (link)
[J3] X. Guo, V. Verma, P. Guerrero, S. Mosanu, M. Stan, “Back to the Future: Digital Circuit Design in the FinFET Era,” Journal of Low Power Electronics (JOLPE), Vol. 13, No. 3, pp. 338–355, DOI 10.1166/jolpe.2017.1489, September 2017. (Invited Paper) (link) (Invited Talk video)
[J2] X. Guo, M. Stan, “Implications of Accelerated Self-Healing as a Key Design Knob for Cross-Layer Resilience”, INTEGRATION, the VLSI journal, DOI 10.1016/j.vlsi.2016.10.008, vol. 56, pp. 167-180, 2017. (pdf)
[J1] M. El-Hadedy, X. Guo, M. Margala, M. Stan, K. Skadron, “Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems.” Journal of Signal Processing Systems (JSPS), DOI 10.1007/s11265-016-1199-1, (2016): 1-18. (pdf)

[C40] Y. Cai, L. Zhu, X. Guo*, “Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing Awareness”, Accepted by Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, January 2025.
[C39] L. Zhu, X. Ma, S. Hao, Y. Pan, X. Guo*, “Elastic EDA: Auto-scaling Cloud Resources for EDA Tasks via Learning-based Approaches”, Accepted by IEEE International Conference on Computer Design (ICCD), Milan, Italy, November 2024.
[C38] Y. Ouyang, W. Yang, H. Wang, Y. Pan*, X. Guo*, “MEGA: A Multimodal EEG-Based Visual Fatigue Assessment System”, Accepted by IEEE Biomedical Circuits and Systems (BIOCAS), Xi’an, China, October 2024.
[C37] L. Zhu, Y. Cai, X. Guo*, “One-for-All: An Unified Learning-based Framework for Efficient Cross-Corner Timing Signoff”, Accepted by ACM/IEEE International Conference on Computer-Aided Design (ICCAD), New Jersey, USA, October 2024.
[C36] C. Morgul, X. Guo*, M. Stan*, “Unveiling Proactive Recovery’s Preventative Impact on NAND Flash Wearout”, Accepted by IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA, July 2024.
[C35] R. Xu, Q. Duan, Q. Chen, X. Guo*, “ILD-MPQ: Learning-Free Mixed-Precision Quantization with Inter-Layer Dependency Awareness”, Accepted by IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Abu Dhabi, UAE, April 2024.
[C34] R. Wang, R. Xu, X. Zhao, K. Jiang, X. Guo*, “CINEMA: A Configurable Binary Segmentation Based Arithmetic Module for Mixed-Precision In-Memory Acceleration”, Accepted by IEEE International Symposium on Circuits & Systems (ISCAS), Singapore, May 2024.
[C33] X. Zhao, T. Wang, R. Jiao, X. Guo*, “Standard Cells Do Matter: Uncovering Hidden Connections for High-Quality Macro Placement”, Accepted by Design, Automation and Test in Europe Conference (DATE), Valencia, Spain, March 2024.
[C32] L. Zhu, X. Guo*, “Delay-Driven Physically-Aware Logic Synthesis with Informed Search”, Accepted by 41st IEEE International Conference on Computer Design (ICCD), Washington DC, USA, November 2023.
[C31] R. Wang, J. Han, M. Stan, X. Guo*, “Hot-LEGO: Architect Microfluidic Cooling Equipped 3DICs with Pre-RTL Thermal Simulation”, Accepted by 15th IEEE International Green and Sustainable Computing Conference (IGSC), co-located with MICRO 2023, Toronto, ON, Canada, October 2023.
[C30] Y. Gu, X. Wang, Z. Chen, C. Wu*, X. Guo*, J. Li, M. Guo, S. Wu, R. Yuan, T. Zhang, Y. Zhang, H. Cai, “Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction”, Accepted by IEEE International Test Conference (ITC), Anaheim, California, USA, October 2023.
[C29] Y. Gao, S. Mosanu, M. Sakib, V. Verma, X. Guo, M. Stan, “LiteAIR5: A System-Level Framework for the Design and Modeling of AI-Extended RISC-V Cores”, 36th IEEE International System-on-Chip Conference (SOCC), Santa Clara, CA, USA, September 2023.
[C28] R. Wang, X. Guo*, “A Hierarchically Reconfigurable SRAM-Based Compute-in-Memory Macro for Edge Computing”, Accepted by International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, June 2023.
[C27] L. Zhu, Y. Gu, X. Guo*, “RC-GNN: A Graph Neural Network Model for Fast and Accurate Signoff Wire Delay Estimation”, Accepted by International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, June 2023.
[C26] X. Zhao, Y. Gao, V. Verma, R. Xu, M. Stan, X. Guo*, “Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units”, ACM Great Lakes Symposium on VLSI (GLSVLSI), Knoxville, TN, USA, June 2023.
[C25] Y. Wei, S. Gong, H. Mei, L. Shi, X. Guo*, “Convolutional Neural Networks on the Edge: A Comparison Between FPGA and GPU”, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, June 2023.
[C24] X. Zhao, R. Xu, X. Guo*, “Post-training Quantization or Quantization-aware Training? That is the Question”, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, June 2023.
[C23] X. Wei, M. El-Hadedy, S. Masanu, Z. Zhu, W. Hwu, X. Guo*, “RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoT”, Accepted by IEEE International System-on-Chip Conference (SOCC), Belfast, Northern Ireland, September 2022. (Best Paper Award)
[C22] M. El-Hadedy⋄, X. Guo⋄*, “ReaLSE: Reconfigurable Lightweight Security Engines for Trusted Edge Devices”, Accepted by IEEE 4th International Conference on Circuits and Systems (ICCS), Chengdu, China, September 2022. (⋄ Equal contributions) (Best Oral Presentation Award)
[C21] M. Morgul, M. Stan, X. Guo*, “Scheduling Active and Accelerated Recovery to Combat Aging in Integrated Circuits”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Virtual, August 2022. (Invited paper)
[C20] M. Morgul, X. Guo, M. Stan, “Towards Everlasting Flash: Preventing Permanent Flash Cell Damage using Circadian Rhythms”, Accepted by IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pafos, Cyprus, July 2022.
[C19] J. Han, X. Guo, K. Skadron, M. Stan, “From 2.5D to 3D Chiplet Systems: Investigation of Thermal Implications with HotSpot 7.0”, accepted by The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (IEEE ITherm), San Diego, USA, June 2022.
[C18] X. Wei, X. Guo*, “Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny Designs”, International Symposium on Quality Electronic Design (ISQED), Virtual, April 2022.
[C17] X. Guo*, “Design-for-Recovery Techniques for Combating Chip Aging Issues”, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, June 2022.
[C16] M. El-Hadedy, X. Guo, W. Hsu, K. Skadron, “Edge Crypt-Pi: Securing Internet of Things with Light and Fast Crypto-Processor,” Proc. of the Future Technologies Conference (FTC), Vancouver, Canada, November 2020. (pdf)
[C15] P. Guerrero, T. Tracy, X. Guo, M. Stan, “Towards low-power machine learning using asynchronous computing with streams,” Proc. of International Green and Sustainable Computing Conference (IGSC), Alexandria, Virginia, October 2019. (pdf)
[C14] P. Guerrero, X. Guo, M. Stan, “ASC-FFT: Area-efficient low-latency FFT design based on asynchronous stochastic computing,” Proc. of IEEE Latin American Symposium on Circuits and Systems (LASCAS), Armenia, Quindío, Colombia, February 2019. (Best Paper Award) (pdf)
[C13] S. Mosanu, X. Guo, M. El-Hadedy, L. Anghel, M. Stan, “Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints”, Proc. of IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM), San Diego, CA, April 2019. (pdf)
[C12] P. Guerrero, X. Guo, M. Stan, “SC-SD: Towards Low Power Stochastic Computing on Sigma Delta Streams,” IEEE International Conference on Rebooting Computing (ICRC), Tysons, VA, November 2018. (Video)(pdf)
[C11] A. Roelke, X. Guo, M. Stan, “OldSpot: A Pre-RTL Model for Fine-grained Aging and Lifetime Optimization,” IEEE International Conference on Computer Design (ICCD), Orlando, FL, October 2018. (pdf) (Github)
[C10] X. Guo, V. Verma, P. Guerrero and M. Stan, “When “things” get older – Exploring Circuit Aging in IoT Applications”, International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 2018. (pdf) (link)
[C9] D. Kamakshi, X. Guo, H. Patel, M. Stan and B. Calhoun, “A Post-Silicon Hold Time Closure Technique using Data-Path Tunable-Buffers for Variation-Tolerance in Sub-threshold Designs”, International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 2018. (pdf) (link)
[C8] S. Eldridge, V. Verma, X. Guo, A. Roelke, K. Swaminathan, N. Chandramoorthy, M. Cochet, A. Buyuktosunoglu, C. Vezyrtzis, R. Joshi, M. Ziegler, M. Stan, P. Bose, “VELOUR – Very Low Voltage Operation Under Resilience Constraints,” The Government Microcircuit Applications and Critical Technology Conference (GOMACTech), Miami, FL, March 2018.
[C7] X. Guo, M. Stan, “Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery,” Proc. of IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Denver, CO, June 2017. (pdf) 
[C6] M. El-Hadedy, X. Guo, M. Stan, K. Skadron, “PPE-ARX: Area- and Power-Efficient VLIW Programmable Processing Element for IoT Crypto-Systems,” Proc. of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Pasadena, CA, July 2017. (pdf)
[C5] X. Guo, M. Stan, “Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery,” Proc. of 13th IEEE Workshop on Silicon Errors in Logic–System Effects (SELSE-13), Boston, MA, March 2017. (Best Paper Award) (pdf)
[C4] X. Guo, M. Stan, “Work hard, sleep well – Avoid irreversible IC wearout with proactive rejuvenation,” Proc. of the ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Macau, China, January 2016. (Acceptance Rate: 94/274 = 34.3%) (pdf) (slides)
[C3] X. Guo, M. Stan, “MCPENS: Multiple-Critical-Path Embeddable NBTI Sensors for Dynamic Wearout Management,” Proc. of 11th IEEE Workshop on Silicon Errors in Logic–System Effects (SELSE-11), pp. 116-121, Austin, TX, April 2015. (pdf) (slides)
[C2] X. Guo, W. Burleson, M. Stan, “Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques,” In Proc. of ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2014. (Acceptance Rate: 174/787 = 22%) (pdf) (.ppt) (poster)
[C1] Y. Zhao, Y. Yang, K. Mazumdar, X. Guo, M.R. Stan, “A Multi-Output on-Chip Switched-Capacitor DC-DC Converter for Near- and Subthreshold Power Modes,” In Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 2014. (pdf) (.ppt)

[T11] “Shift-Left in EDA: From Architecture to Signoff” at Huawei-Fudan Semiconductor Technology Forum, Shanghai, China, December 2022.
[T10] “SoC Design in the Era of AI: Architecture, EDA and Packaging” at Aijishu Open Course, Virtual, China, August 2022. (Recording)
[T9] “EDA Challenges in the “Shift-Left” Regime”, at Huawei Shanghai Research Center, Virtual, China, August 2022.
[T8] “Vitis-AI Powered Intramuscular Site Detection for Autonomous Injection” at Zhidongxi Open Course – AMD-Xilinx joint event, Virtual, China, June 2022. (Recordings)
[T7] Chip Design in the 21st Century: The Intersection of Everything” at UM-SJTU JI/GIFT Graduate Student Seminar, Shanghai, China, May 2022.
[T6] “Shift Left: A Designer’s Perspective” at Huawei Strategy and Technology Workshop (STW), Shenzhen, China, October 2021.
[T5] “Cross-layer Co-design for Resilient Hardware” at Boston (and Beyond) Area Architecture Workshop (BARC),Online, January 2021.
[T4] “High Speed and Low Power SoC Design and EDA Challenges” at UM-SJTU Joint Institute International Symposium for Young Investigators, Online, June 2020.
[T3] “Reliable and Low Power Digital Circuits and Systems” at IMEC, Online, January 2018.
[T2] “Towards Wearout-aware and Accelerated Self-Healing Digital Systems,” at Ayar Lab, San Francisco, CA, October 2017.
[T1] “Towards Wearout-aware and Accelerated Self-Healing Digital Systems,” at Intel, Hillsboro, OR, December 2016.

[W18] R. Wang, X. Guo, “A Multi-Functional SRAM-Based Compute-in-Memory Macro on the Edge”, Semiconductor Technology Forum 2022, Shanghai, December 2022. (Best Paper Award)
[W17] X. Zhao, X. Guo, “DAG-MP: Enabling High-Quality Macro Placement with Enhanced Dataflow-Aware Guidance”, Semiconductor Technology Forum 2022, Shanghai, December 2022.
[W16] R. Wang, X. Guo, “An All-Digital Reconfigurable SRAM-Based Compute-in-Memory Macro for TinyML Devices”, TinyML Asia, Virtual, November 2022.
[W15] X. Zhao, V. Verma, Y. Gao, R. Xu, M. Stan, X. Guo, “TILE-MPQ: Design Space Exploration of Tightly Integrated Layer-WisE Mixed-Precision Quantized Units for TinyML Inference”, TinyML Asia, Virtual, November 2022.
[W14] X. Guo, X. Zhao, V. Verma, M. Stan, “Extending RISC-V ISA for Tightly Integrated Inference at the Edge”, RISC-V Summit China 2022 (RVSC2022), Virtual, August 2022. (Recording)
[W13] M. Stan, K. Skadron, X. Guo, J. Han, “HotSpot Through the Ages”, HotSpots Strike Back Workshop (HSSB), co-located with International Symposium on Computer Architecture (ISCA), New York, NY, June 2022.
[W12] R. Wang, Y. Gu, X. Guo, “J-Eye: Intramuscular Site Detection for Autonomous Injection using Vitis AI”, Accepted by IEEE International NEWCAS Conference (NEWCAS) Student Workshop, Quebec, Canada, June 2022.
[W11] M. Morgul, X. Guo, M. Stan, “Circadian Rhythm: A Candidate for Achieving Everlasting Flash Memories”, Proceeding of the 13th Annual Non-Volatile Memories Workshop (NVMW), San Diego, CA, May 2022.
[W10] X. Guo, “Cross-layer Codesign for Resilient Hardware”, Boston (and Beyond) Area Architecture Workshop (BARC), Online, January 2021.
[W9] S. Mosanu, X. Guo, M. El-Hadedy, L. Anghel, M. Stan, “AES and SHA Cryptography Library for Chisel,” Chisel Community Conference (CCC), Berkeley, CA, November 2018. (Youtube) (Github)
[W8] V. Verma, X. Guo, M. Stan, “Low-Power Design with Open-Source Hardware: Opportunities and Challenges,” Workshop on Open-Source EDA Technology (WOSET), co-located with ICCAD, San Diego, CA, November 2018. (link) (pdf)
[W7] M. El-Hadedy, X. Guo, X. Huang, M. Margala, “RE-HASE: Regular-Expressions Hardware Synthesis Engine,” Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC’17), in conjunction with SC, Denver, CO, November 2017. (pdf) (slides)
[W6] S. Eldridge, K. Swaminathan, N. Chandramoorty, A. Buyuktosunoglu, A. Roelke, X. Guo, V. Verma, R. Joshi, M. Stan, P. Bose, “A low voltage RISC-V heterogeneous system: boosted SRAMs, machine learning and fault injection on VELOUR,” Workshop on Computer Architecture Research with RISC-V (CARRV), co-located with IEEE MICRO, Boston, MA, October 2017. (pdf)
[W5] M. El-Hadedy, X. Guo, W. Hwu, M. Stan, K. Skadron, “Crypt-Pi: A Light and Fast Crypto-Processor for IoT Applications,” SRC TECHCON, Austin, TX, September 2017. (Best-in-Session Award)
[W4] M. El-Hadedy, X. Guo, M. Stan, K. Skadron, W. Hwu, “R-NNPE: Reconfigurable Neural Network Processing Elements,” SRC TECHCON, Austin, TX, September 2017.
[W3] D. Akella, X. Guo, M. Stan, B. H. Calhoun, “Enabling Post-Silicon Hold Time Closure by Tunable-Buffer Insertion,” Design Automation Conference (DAC), Work-in-Progress (WIP) Poster Session, Austin, TX, June 2017.
[W2] X. Guo, M. Stan, “Enabling Wearout-Immune BEOL and FEOL with Active Rejuvenation,” Proc. of the IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), in conjunction with ICCAD, Austin, TX, November 2016. (pdf) (poster) (link)
[W1] X. Guo, M. Stan, “Towards Wearout-Free Systems: A Self-Healing Strategy Enabled by Accelerated and Active Recovery,” SRC TECHCON, Austin, TX, September 2016.

[WP] K. Mazumdar, X. Guo, R. Zhang, M. Stan, “Charge-Recycled Power-Regulation with Stacked Loads and Stacked Switched-Capacitors”.
[WP]  V. Verma, X. Guo, S. Mosanu, M. Das, Y. Chen, B. Ghaemmaghami, M. Stan, “Towards Low-Power Open Source Hardware: Methodology, Design Techniques and Lessons”.