Xinfei Guo, Ph.D. (郭鑫斐)
Assistant Professor, Ph.D. Advisor
University of Michigan – Shanghai Jiao Tong University Joint Institute (UM-SJTU JI)
Shanghai Jiao Tong University
Office: Room 419, Longbin Building, 800 Dong Chuan Road, Shanghai, China 200240 (Map)
Lab: Room 212-11B, Longbin Building, 800 Dong Chuan Road, Shanghai, China 200240 (Map)
Email: xinfei.guo [at] sjtu [dot] edu [dot] cn
Tel: +86-21-3420-6765 Ext. 4191


About Me

I am currently an assistant professor and PhD Advisor at UM-SJTU Joint Institute (JI) at Shanghai Jiao Tong University, where I am leading the Intelligent Circuits, Architectures, and Systems (iCAS) Lab at SJTU. I received my Ph.D. in Computer Engineering from the University of Virginia, where I was part of the High-performance Low-power (hplp) Lab led by Prof. Mircea Stan. I also hold a M.S. degree in Electrical and Computer Engineering from the University of Florida and a B.Eng degree from Xidian University. Before joining JI, I was a Senior SoC Design Engineer at NVIDIA (US), where I contributed to the first few generations of industry-leading BlueField® Data Processing Unit (DPU). I also worked at IBM Thomas J. Watson Research Center as an adjunct researcher. A blend of academia and industry experiences led to my current focus of research, which is on low power and intelligent chip system design, smart electronic design automation (EDA), novel microarchitectures and machine learning accelerators. My previous research projects have resulted in seven chip tapeouts (including 14nm and 7nm), over 30 peer-reviewed research papers and a book. My work was also recognized by 3 best paper awards (LASCAS 2019, SELSE 2017, SRC TECHCON 2017), an IEEE CASS Fellowship and several other research awards. I am an Associate Editor for Integration, the VLSI Journal, and have served as PC member or chair positions for over 30 international conferences, such as DAC, CICC, ICCAD, ASPDAC, FCCM, HOST, ASAP. I am a Senior Member of the IEEE, an ACM member, a CCF member and the co-founder and co-chair for the IEEE SSCS Webinars for Young Excellence (WYE) program. For the current semester (SU22), I teach VE470 Computer Architecture.

🔬 Research Interests

  • AI/Machine learning-assisted chip design automation techniques
  • Energy-efficient & reliable chip design for sustainable computing
  • Hardware acceleration with FPGAs and GPUs
  • System-on-chip design with ARM/RISC-V CPUs
  • Advanced packaging techniques (Chiplet, 3DIC)
🆕 Recent News

  • 06/2022 [Research] Our J-Eye team presented the work at the Zhidongxi Open Course (智东西公开课), a recording is available here.
  • 05/2022 [Research] I gave a talk “Chip Design in the 21st Century: The Intersection of Everything” as part of UM-SJTU JI/GIFT Graduate Seminar Series.
  • 04/2022 [Research] Congrats to my students Runxi and Yuqi for receiving the prestigious inaugural “Women in Technology” award (The only team in this category) from the AMD-Xilinx Adaptive Computing Challenge 2021!  (Xilinx News) (SJTU News) (JI News) (Competition) (Project)
  • 04/2022 [Service] I hosted the IEEE Solid State Society (SSCS) Webinar for Young Excellence (WYE) “Grant Proposal Writing Tips and Strategies: Securing Funds for your Brilliant Research Idea”. The recording is available here.
  • 04/2022 [Research] Our work on developing agile framework for AES (named Agile-AES) has been accepted by Integration!
  • More News…
🔥 To Prospective Graduate Students

I am actively looking for self-motivated graduate students (Masters & Ph.D.)  to work with me to tackle the most challenging yet practical research problems in the field of digital VLSI design, Electronic Design Automation (EDA) or Computer Architecture. Please don’t hesitate to send me an email with your latest CV/transcript.

📢 To SJTU Undergraduate Students

I am always looking for self-motivated undergraduate researchers (who can start asap) to work on projects in the field of low power chip design, machine learning assisted chip design automation and hardware acceleration techniques. You can also take credits (through VE490) or participate through other university level research programs (such as IPP, PRP or CTP). Compensation is available for those who are eligible. You will have opportunities to publish at top conferences and journals (as the first author), and will also gain practical skills in digital design, large-scale SoC design with advanced technology node, machine learning or the whole chip design process in an industry-like research environment. Please feel free to stop by or send me an email with your latest CV/transcript.