Xinfei Guo, Ph.D. （郭鑫斐）
University of Michigan – Shanghai Jiao Tong University Joint Institute (UM-SJTU JI)
Shanghai Jiao Tong University
Office: Room 419, Longbin Building, 800 Dong Chuan Road, Shanghai, China 200240 (Map)
Lab: Room 212-11B, Longbin Building, 800 Dong Chuan Road, Shanghai, China 200240 (Map)
Email: xinfei.guo [at] sjtu [dot] edu [dot] cn
Tel: +86-21-3420-6765 Ext. 4191
I am currently an Associate Professor at UM-SJTU Joint Institute (JI) at Shanghai Jiao Tong University, where I am leading the Intelligent Circuits, Architectures, and Systems (iCAS) Lab at SJTU. I received my Ph.D. in Computer Engineering from the University of Virginia, where I was part of the High-performance Low-power (hplp) Lab led by Prof. Mircea Stan. I also hold a M.S. degree in Electrical and Computer Engineering from the University of Florida and a B.Eng degree from Xidian University. Before joining JI, I was a Senior SoC Design Engineer at NVIDIA (US), where I contributed to the first few generations of industry-leading BlueField® Data Processing Unit (DPU). I also worked at IBM Thomas J. Watson Research Center as an adjunct researcher. A blend of academia and industry experiences shaped my current focus of research, which is on low power and intelligent chip system design, smart electronic design automation (EDA), novel microarchitectures and accelerators. My previous research projects have resulted in seven chip tapeouts (including 14nm and 7nm), over 40 peer-reviewed research papers and a book. Our work were also recognized by several best paper awards (e.g. SOCC 2022, LASCAS 2019, SELSE 2017, etc), an IEEE CASS Fellowship and several other research awards. I am an Associate Editor-in-Chief for the IEEE Transactions on Very Large Scale Integration Systems (TVLSI) and an Associate Editor for Elsevier Integration, the VLSI Journal, and have served as PC member or chair positions for over 30 international conferences, such as DAC, CICC, ICCAD, ASPDAC, FCCM, HOST, SOCC. I am a Senior Member of the IEEE and the CCF, an ACM member, and the co-founder and co-chair for the IEEE SSCS Webinars for Young Excellence (WYE) program. I frequently teach computer engineering courses such as ECE4700J Computer Architecture and ECE4810J SoC Design.
🔬 Research Interests
- AI/Machine learning-assisted Chip Design Automation Techniques
- Energy-efficient & Reliable Chip Design for Sustainable Computing
- Reconfigurable Computer Architecture
- System-on-chip design with ARM/RISC-V CPUs
- Advanced packaging techniques (Chiplets, 3DIC)
🆕 Recent News
- 08/2023 [Research] Our recent work on intelligent macro placement was accepted by DATE 2024!
- 10/2023 [Service] Elevated to CCF Senior Member.
- 08/2023 [Research] Our recent work on physically-aware synthesis was accepted by ICCD 2023!
- 06/2023 [Service] The SSCS Webinars for Young Excellence (WYE) efforts for 2022 were summarized here.
- 04/2023 [Service] I was appointed as the Associate Editor-in-Chief of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI). We welcome your submission!
- More News…
🎓To Post-doc Candidates
I have 1-2 openings for Post-doc researchers who are interested in one or more of the following research areas:
- Electronic Design Automation
- Low-power Circuit and Architectures
- HW/SW co-design for Edge AI
- Circuit Reliability
- Advanced Packaging (Chiplet, 3DIC)
Interested candidates can send your updated CV together with 3 representative publications to Dr. Xinfei Guo via email@example.com with the following subject line: [Post-Doc Application] + First Name+Last Name.
🔥 To Prospective Graduate Students
I am actively looking for self-motivated graduate students (Masters & Ph.D.) to work with me to tackle the most challenging yet practical research problems in the field of digital VLSI design, Electronic Design Automation (EDA) or Computer Architecture. Please don’t hesitate to send me an email with your latest CV/transcript.
📢 To SJTU Undergraduate Students
I am always looking for self-motivated undergraduate researchers (who can start asap) to work on projects in the field of low power chip design, machine learning assisted chip design automation and hardware acceleration techniques. You can also take credits (through VE490) or participate through other university level research programs (such as IPP, PRP or CTP). Compensation is available for those who are eligible. You will have opportunities to publish at top conferences and journals (as the first author), and will also gain practical skills in digital design, large-scale SoC design with advanced technology node, machine learning or the whole chip design process in an industry-like research environment. Please feel free to stop by or send me an email with your latest CV/transcript.