Welcome to Efficient and High Performance Computing Lab at SJTU!
We are a group of people working at the intersection areas of computer architecture, digital circuit design, and low-level software, for efficient, fast, and reliable computing.
Recent News
[Mar 2025] One paper is accepted to DAC 2025. The work is about Efficient and Flexible Systolic Array for Neural Network Inference.
[Feb 2025] Three papers are accepted to RTAS 2025. Two papers are about real-time scheduling on heterogeneous computing architecture. One paper is about the real-time scheduling for cyber-physical system.
[Jan 2025] Dr. An Zou is promoted to associate professor.
[Nov 2024] Four papers are accepted to DATE 2025. One paper is about the fine-grained power management for GPU. Two papers are about real-time scheduling on heterogeneous computing architecture. One paper is about the simulating platform for heterogeneous computing architecture.
[Oct 2024] We received fundings (1.41M RMB) to research on the Hardware Circuit Integrity Protection based on Power Delivery Network Characteristics.